Digital Back end and Verification Engineer

Job Code: 3098
Business Address/ Job Location:
Unit 601, 1726 Dolphin Ave. Kelowna, V1Y 9R9 

Degree Requirements: BSEE, with 2 years of experience.

Our Location

Our Kelowna Design Center is located in the heart of the Okanagan Valley, a region 

known for its wineries, long hot summers and exceptional skiing. We offer the unique opportunity to design and develop highly integrated, mixed signal circuits for audio/video consumer electronics applications in one of the most beautiful locations in North America. 

About ESS Technology

 Our knowledge with signal converters has lead to some of the world’s best audio DACs and ADCs. This expertise along with a “hands-on” approach to all aspects of IC design, gives a working environment and quality of life that is second to none.  

Areas of Responsibility

Our IC’s are based on state-of-the-art CMOS technologies (0.15-um and down) containing large digital blocks and precision analog circuits. As a Digital Back end and Verification Engineer, you are interested in working in a dynamic team environment where innovation is highly regarded, and you will be skilled in the execution of the back-end processes including synthesis, place and route, and simulation of post routed netlists. Your responsibilities will include floor planning, placement, test logic insertion, clock tree synthesis, routing, post-route timing and crosstalk noise analysis, as well as running time domain simulations of the realized designs.  Drawing upon your work experience, you will be able to identify and fix design issues such as antenna, LVS and timing issues using tools such as Synopsys Astro, Mentor Graphics Calibre and Modelsim.

The successful candidate will be able to perform the backend process with a minimal amount of supervision and be capable of working in a team environment. Must have strong previous work experience with Synopsys Astro, Cadence Virtuoso, and Calibre DRC/ERC and LVS/ANT as well as a Verilog timing simulator such as Modelsim.  Proficiency in the Verilog language is required, and the successful candidate will be comfortable with modern simulation and synthesis tools.  An in depth understanding of DFT, Scan Insertion, Sythesis, Place and Route, Synopsys timing constraints and understanding of Simulation and Verification flows of post routed design are a must.

Please submit your Resume to hr@esstech.com 


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